Lines Matching refs:IRQ

14 Secondly, the IRQ subsystem.
37 SA1111 IRQ handler, SA1111 IRQs can hold off SMC9196 IRQs indefinitely.
46 We also bring the idea of an IRQ "chip" (mainly to reduce the size of
55          * Acknowledge the IRQ.
56          * If this is a level-based IRQ, then it is expected to mask the IRQ
61          * Mask the IRQ in hardware.
65          * Unmask the IRQ in hardware.
69          * Re-run the IRQ
73          * Set the type of the IRQ.
84          the hardware IRQ if possible.  If not, may call the handler
86 type   - optional.  If you don't support changing the type of an IRQ,
88          set the IRQ type.
90 For each IRQ, we keep the following information:
93         - flags indicating what we can do with this IRQ (valid, probe,
95         - status of the IRQ (probing, enable, etc)
97         - per-IRQ handler
104 "edge" knows about the brokenness of such IRQ implementations - that you
105 need to leave the hardware IRQ enabled while processing it, and queueing
106 further IRQ events should the IRQ happen again while processing.  The
122                 Set the mask/unmask methods for handling this IRQ
126                 Set the handler for this IRQ (level, edge, simple)
130                 Set a "chained" handler for this IRQ - automatically
131                 enables this IRQ (eg, Neponset and SA1111 handlers).
139                 Set active the IRQ edge(s)/level.  This replaces the
149    parent IRQ via the correct chip specific function.  For instance, if
151    acknowledge the SA1110 IRQ each time you re-read the SA1111 IRQ status.
153 6. For any child which doesn't have its own IRQ enable/disable controls
154    (eg, SMC9196), the handler must mask or acknowledge the parent IRQ
157    the parent IRQ should be unmasked, and the status of all children must
158    be re-checked for pending events.  (see the Neponset IRQ handler for
166 solution can't provide the full answer to low IRQ latency.