Lines Matching refs:PCI

23 The MSI capability was first specified in PCI 2.2 and was later enhanced
24 in PCI 3.0 to allow each interrupt to be masked individually.  The MSI-X
25 capability was also introduced with PCI 3.0.  It supports more interrupts
37 Pin-based PCI interrupts are often shared amongst several devices.
44 arrived in memory (this becomes more likely with devices behind PCI-PCI
47 the interrupt.  PCI transaction ordering rules require that all the data
53 PCI devices can only support a single pin-based interrupt per function.
66 PCI devices are initialised to use pin-based interrupts.  The device
81 Most of the hard work is done for the driver in the PCI layer.  It simply
82 has to request that the PCI layer set up the MSI capability for this
251 Calling this function asks the PCI subsystem to allocate any number of
451 MSI-X Table.  This address is mapped by the PCI subsystem, and should not
472 This is a requirement of the PCI spec, and it is enforced by the
473 PCI layer.  Calling pci_enable_msi_range() when MSI-X is already
518 Several PCI chipsets or devices are known not to support MSIs.
519 The PCI stack provides three ways to disable MSIs:
541 Some PCI bridges are not able to route MSIs between busses properly.
545 PCI configuration space (especially the Hypertransport chipsets such
554 where $bridge is the PCI address of the bridge you've enabled (eg
583 to bridges between the PCI root and the device, MSIs are disabled.